The present invention relates to integrated circuits and, more particularly, to fabrication of a bipolar transistor. A major objective of the present invention is to provide a high-performance bipolar transistor in which a "hot-carrier effect" is minimized.
Much of modern technological progress is associated with advances in semiconductor processing technology that have provided greater speed and integration in electrical circuits. The basic building blocks of these circuits are transistors, which typically serve as electric switches, detectors and amplifiers. Of several alternative transistor processing technologies, of primary interest herein is BiCMOS, which integrates bipolar and CMOS technology. In a BiCMOS device, bipolar transistors typically use oxide isolation over a base region; the oxide isolation subjects the transistors to a hot-carrier effect that impairs the performance. The hot-carrier effect also impairs non-BiCMOS bipolar transistors using oxide isolation. However, some non-BiCMOS technologies use junction isolation and do not suffer from this effect.
A bipolar transistor comprises a p-type base sandwiched between an n-type emitter and an n-type collector. Under a forward bias, the collector is at a higher potential than the emitter. No electron current flows from the emitter to the collector unless there is a base current. A small base current induces an electron avalanche to flow from the emitter to the collector. The ratio of the emitter current I.sub.e to the base current I.sub.b is referred to as the transistor gain .beta., an important performance parameter for a bipolar transistor.
A typical bipolar transistor includes a subcollector in the form of a heavily doped n-type region in a p-type silicon substrate. The subcollector is buried by a p-type epitaxial silicon layer. The region of the epitaxial silicon layer above the subcollector is moderately doped n-type to define a collector drift region. An upper sublayer of the collector drift region is doped p-type to define an intrinsic base. An epi-emitter can be formed by heavily implanting a localized region of the intrinsic base with n-type dopant. Higher performance can be attained using an alternative poly-emitter: polysilicon is deposited over the epitaxial layer; the polysilicon is patterned to define a polysilicon emitter structure; the polysilicon emitter structure is heavily doped n-type; and the implant is driven through the polysilicon emitter structure into the epitaxial layer below so that the poly-emitter includes a polysilicon emitter section and a very shallow epitaxial emitter section.
Access to the intrinsic base is provided by an extrinsic base, located laterally of the emitter. The extrinsic base is heavily doped p-type and is spaced from the emitter to prevent a short between two heavily doped regions of opposite conductivity types. Access to the subcollector is provided by a heavily doped n-type collector sink, also laterally spaced from the emitter. A link-base section of the intrinsic base between the emitter and the extrinsic base can be more heavily doped than a center-base section of the intrinsic base below the emitter. When the link-base section of the intrinsic base is more heavily doped, it is commonly referred to as a "link base". The heavier doping reduces base resistance and consequently increases transistor gain .beta..
To achieve a forward bias, a positive potential is applied to the subcollector through the collector sink and a negative potential is applied to the emitter. A base current is introduced to the intrinsic base through the extrinsic base. The base current induces an emitter current of electrons flowing generally toward the collector. Some of the emitter electrons combine with holes in the base and never reach the collector. These recombinations impair performance.
Recombinations are more likely when electrons travel through more heavily doped p-type regions and wheless likely when electrons travel shorter distances through a lightly doped base. These conditions are attained by electrons that travel straight down from the emitter through the center base region to the collector drift region.
Not all electrons travel straight down. Some electrons exit the emitter laterally and travel a circuitous path through the link-base section to the collector. The longer path through the link-base section results in more recombinations and lower gain, especially in cases where the link-base section is more heavily doped than the center-base section. The hot-carrier effect causes a higher percentage of electrons to exit the emitter laterally into this link-base section. Thus, more recombinations occur and performance is degraded.
The hot-carrier effect is established while a bipolar transistor is reversed biased. Reverse biasing can occur temporarily during a transistor transition in which the base potential falls more rapidly than the emitter potential. Under reverse bias, the emitter is at a higher potential than the base. Electrons are drawn from the extrinsic base through the link-base section and toward the emitter. The electric field is the strongest at the junction between the emitter and the intrinsic base. At this boundary, electrons endure the greatest acceleration. Scattering can direct some of the electrons toward the oxide above the link-base section. Normally, a potential barrier at the junction between the oxide and the link-base section is sufficient to prevent entry of electrons into the oxide. However, when the reverse-bias field is strong enough, these electrons can have enough energy to jump the potential barrier and travel into the oxide. Having lost some energy in the process, the electrons are trapped in the oxide. In the process of jumping the potential barrier, the electrons introduce defects in the junction, lowering the barrier and making it easier for more electrons to be trapped in the oxide.
The trapped electrons establish an electric field that attracts positive charges that accumulate in the epitaxial layer near the oxide. When a forward bias is applied to the transistor, electrons exiting the emitter can be attracted by the gathered positive charges. Thus more electrons exit laterally from the emitter and those that travel laterally spend more time near the upper potions of the link-base section, near the oxide. Here they can cross the impaired oxide barrier and be trapped or they can recombine with the accumulated positive charges. Collectively, these effects decrease the percentage of electrons reaching the collector. As a result, transistor gain .beta. is diminished.
A laterally graded emitter can be used to reduce the hot-carrier effect as disclosed by Honda et al. in "Suppression of Hot Carrier Effects by Laterally Graded Emitter (LGE) Structure in BiCMOS", IEDM Technical Digest, 1990, pp. 227-230. In the LGE approach, a lightly doped n-type region extends from a heavily doped n-type epi-emitter into a lightly doped p-type link-base section of an intrinsic base between the epi-emitter and the extrinsic base. The p/n junction is thus between two lightly doped regions, resulting in a smaller peak field strength. Thus, electrons undergo less acceleration and are less likely to be injected into the oxide. Thus, the hot-carrier effect is reduced and performance impairment is diminished.
Formation of the disclosed laterally graded emitter is as follows. An emitter opening is defined in a silicon dioxide mask. A light n-type implant is made. An oxide sidewall is then grown on the mask. Then a heavy n-type implant is made. The result is a heavily doped n-type epi-emitter inside a lightly doped n-type lateral emitter.
While the LGE approach does reduce the hot-carrier effect, further reductions are desired. In addition to its limited effectiveness, the LGE approach suffers from incompatibility with two recognized performance enhancements for bipolar transistors. First, as indicated above, a link-base section more heavily doped than the center-base section can reduce base resistance and improve the transistor gain .beta.. However, increasing link-base doping increases the field at the LGE p/n junction, increasing the hot-carrier effect. Hence the LGE approach imposes a conflict between decreased base resistance and decreased hot-carrier effect.
Second, the LGE method for fabricating a bipolar transistor is not compatible with the poly-emitter approach. There is no suggestion as to how one would position a polysilicon emitter structure with appropriate precision between the light emitter implant and the subsequent heavy emitter implant.
Third, the LGE method is prone to defective junctions between the emitter and the intrinsic base. Since a light implant precedes a heavy implant, there is a likelihood that the light implant will be driven deeper than the heavy implant. The result is an emitter that is not only laterally graded, but also vertically graded. The vertically graded emitter would result in a less effective injection of electrons into and through the intrinsic base, impairing performance.
What is needed is a bipolar transistor and a method for making the bipolar transistor that minimizes the hot-carrier effect, while providing compatibility with BiCMOS processing, including the fabrication of established performance features. In particular, poly-emitters and link-bases should be employable without compromising the effectiveness of hot-carrier effect reduction. Finally, the transistor and method should avoid the problem of a vertically graded emitter and provide a relatively sharp junction between the base and emitter.